1. Field of the Invention
The present invention relates to a CMOS (complementary metal oxide silicon) image sensor. More specifically, the present invention relates to a CMOS image sensor and a method for manufacturing the same, capable of simplifying the structure of the CMOS image sensor while achieving scale down of a pixel.
2. Description of the Related Art
In general, an image sensor is a semiconductor device for converting optical images into electric signals, and it may be classified as a charge coupled device (CCD) or a CMOS image sensor.
The CCD has a plurality of photodiodes (PDs), which are arranged in the form of a matrix in order to convert optical signals into electric signals. The CCD includes a plurality of vertical charge coupled devices (VCCDs) provided between photodiodes and vertically arranged in the matrix so as to transmit electrical charges in the vertical direction when the electrical charges are generated from each photodiode, a plurality of horizontal charge coupled devices (HCCDs) for transmitting the electrical charges from the VCCDs in the horizontal direction, and a sense amplifier for outputting electric signals by sensing the electrical charges being transmitted in the horizontal direction.
However, CCDs may have has various disadvantages, such as a complicated drive mode, high power consumption, and so forth. Also, the CDD is generally manufactured using multi-step photo processes, so the manufacturing process for the CCD can be complicated.
In addition, since it can be difficult to integrate certain circuits, such as a controller, a signal processor, and an analog/digital converter (AID converter) onto a single chip of the CCD, the CCD may not be advantageous for compact-size products.
Recently, the CMOS image sensor has been spotlighted as a next-generation image sensor capable of solving certain problems of the CCD.
The CMOS image sensor is a device employing a switching mode to sequentially detect an output of each unit pixel using MOS transistors, in which the MOS transistors are formed on a semiconductor substrate corresponding to the unit pixels through a CMOS technology. CMOS image sensors may also use peripheral devices, such as a controller and a signal processor.
That is, the CMOS sensor includes a photodiode and at least one MOS transistor in each unit pixel, and sequentially detects the electric signals of each unit pixel in a switching mode to realize images.
Since the CMOS image sensor makes use of the CMOS technology, the CMOS image sensor has advantages such as relatively low power consumption and a relatively simple manufacturing process with fewer photo processing steps.
In addition, the CMOS image sensor allows the product to have a compact size, because peripheral circuits such as a controller, signal processor, and A/D converter can be integrated onto the CMOS image sensor chip.
Therefore, CMOS image sensors have been extensively used in various applications, such as digital still cameras, digital video cameras, and so forth.
The CMOS image sensor is classified into a 3Tr-1PD type image sensor, 4Tr-1PD type image sensor, and 5Tr-1PD type image sensor depending on the number of transistors per unit pixel. The 3Tr-1PD type image sensor includes one photodiode and three transistors per unit pixel and the 4Tr-1PD type image sensor includes one photodiode and four transistors per unit pixel.
Hereinafter, description will be made in relation to a lay-out of a unit pixel and an equivalent circuit of a conventional 3Tr-1PD type image sensor.
FIG. 1 is an equivalent circuit schematic of the conventional 3Tr-1PD type image sensor, and FIG. 2 is a layout view illustrating the unit pixel of the conventional 3Tr-1PD type image sensor.
As shown in FIG. 1, the unit pixel of the conventional 3Tr-1PD type image sensor includes one photodiode PD and three NMOS transistors T1, T2 and T3.
A cathode of the photodiode PD is connected to a drain of the first nMOS transistor T1 and a gate of the second nMOS transistor T2.
In addition, sources of the first and second nMOS transistors T1 and T2 are connected to a power line that feeds a reference voltage VR, and a gate of the first nMOS transistor T1 is connected to a reset line that feeds a reset signal RST.
A source of the third NMOS transistor T3 is connected to a drain of the second nMOS transistor T2, a drain of the third nMOS transistor T3 is connected to a readout circuit (not shown) through a signal line, and a gate of the third nMOS transistor T3 is connected to a column select line that feeds a selection signal SLCT.
The first nMOS transistor T1 is a reset transistor Rx for resetting optical charges collected in the photodiode PD, the second nMOS transistor T2 is a source follower transistor Dx serving as a source follower buffer and/or amplifier, and the third NMOS transistor T3 is a select transistor Sx performing switching and addressing functions.
As shown in FIG. 2, an active area 10 is defined on the unit pixel of the conventional 3Tr-1PD type image sensor, so that one photodiode 20 is formed in a large-width part of the active area 10, and gate electrodes 30, 40 and 50 of three transistors T1, T2 and T3 overlap remaining parts of the active area 10, respectively.
That is, the reset transistor Rx corresponds to the gate electrode 30, the source follower transistor Dx corresponds to the gate electrode 40, and the select transistor Sx corresponds to the gate 50.
Dopants are implanted into the active area 10 of each transistor, except for portions below the gate electrodes 30, 40 and 50, thereby forming source/drain areas of each transistor.
Thus, an input terminal Vin that receives an external potential is provided in the source/drain area formed between the reset transistor Rx and the source follower transistor Dx, and an output terminal Vout which is connected to a readout circuit (not shown) is provided in the source/drain area formed at one side of the select transistor Sx.
FIG. 3 is a sectional view taken along line IV-IV′ of FIG. 2 showing the conventional CMOS image sensor.
As shown in FIG. 3, the conventional CMOS image sensor includes an isolation layer 102 formed in an isolation area of a p-type semiconductor substrate 101 on which the active area and the isolation area are defined, a source follower transistor having a gate electrode 103 extending across a part of the isolation layer 102 and the active area, a photodiode area (PD) 105 formed on a part of the active area of the semiconductor substrate 101, a dielectric layer 45 formed on the entire surface of the semiconductor substrate 101, and a metal interconnection 46 on the dielectric layer 45 so as to electrically connect the gate electrode 103 with the photodiode area 105.
The metal interconnection 46 connects the gate electrode 103 with the photodiode area 105 through tungsten plugs 48 in contact holes formed through the dielectric layer 45 such that predetermined portions of surfaces of the gate electrode 103 and the photodiode area 105 are exposed.
According to the conventional CMOS image sensor having the above structure, since the photodiode area 105 is electrically connected to the gate electrode 103, a potential variation in the photodiode area 105 may exert an influence upon the gate potential of the source follower transistor Dx (see FIG. 1).
In addition, the gate potential may exert great influence upon the performance of the transistor.
However, in order to maximize the characteristics of the image sensor, it is necessary to directly transfer the potential variation of the photodiode area to a gate terminal of an adjacent transistor without potential loss.
Therefore, differently from other devices, a method of connecting a photodiode area to a gate electrode of an adjacent transistor is very important.
As mentioned above, according to the conventional connection method, contact holes are formed at upper portions of the photodiode area and the gate, and then tungsten plugs are formed by filling the contact holes with metallic materials. In this state, a metal layer such as an aluminum layer is deposited thereon and patterned to form a metal interconnection (e.g., metal interconnection 46 in FIG. 3).
However, the above connection method may cause damage to the photodiode when forming the contact hole in the photodiode area. In addition, since the photodiode area is connected to the gate electrode by means of the metal interconnection through four ohmic contacts, it can be challenging to improve the pixel design margin.